1. Field of the Invention
The present invention relates to telephone systems and, more particularly, to a technique for preventing data stored in a memory of a telephone system from being corrupted during a power failure.
2. Description of the Related Art
In a telephone system, important data which must be stored in a memory even during a power failure is generally backed up by a battery. As a memory, a SRAM (static random access memory) which is easily available in the market is widely used.
In an earlier circuit for storing data of a memory of a telephone system during a power failure, the memory receives an address, data, a read signal and a write signal from a processor. A chip enable terminal of the memory is connected to an output terminal of an OR gate. The OR gate has one terminal connected to a memory enable signal and has another terminal connected through an inverter to an output of a voltage sensing circuit. A decoder receives signals from the processor and generates the memory enable signal. In order to store important data even during a power failure, a power source is applied through an external battery to the inverter and to the OR gate and the decoder. During the power failure, the data stored in the memory as prevented for being overwritten and corrupted by disabling the chip enable terminal of the memory in response the output of the voltage sensing circuit.
The following patents each disclose features in common with the present invention but do not teach or suggest a circuit for preventing data stored in the memory for being corrupted which includes a decoder connected to a chip enable terminal of the memory and includes a voltage sensing circuit connected to a chip enable terminal of the decoder from disabling the memory during an abnormal operation voltage range as recited in the present claims.
______________________________________ PATENT NO. INVENTOR DATE ______________________________________ .cndot. 5,418,841 Haraguchi et al. May 23, 1993 .cndot. 5,241,591 Saji August 31, 1993 .cndot. 5,182,769 Yamaguchi et al. January 26, 1993 .cndot. 5,042,066 Ikefuji August 20, 1991 .cndot. 5,014,308 Fox May 7, 1991 .cndot. 4,961,220 Tentler et al. October 2, 1990 .cndot. 4,653,088 Budd et al. March 24, 1987 .cndot. 4,509,201 Sekigawa et al. April 2, 1985 .cndot. 4,488,006 Essig et al. December 11, 1984 .cndot. 4,197,432 Tiedt April 8, 1980 ______________________________________
However, since the external battery supplies power to many logic circuits even during the power failure, the current consumed is increased and the capacity of the battery is increased in proportion thereto, thereby raising production costs. Furthermore, an operation time is increased due to the operation of the inverter and the OR gate and the circuit becomes complicated.